1. Field of the Disclosure
The present invention relates to liquid crystal display devices, and more particularly to device and method for controlling a reference voltage of a digital-to-analog converter for minimizing variation of output voltages among LED driving chips which drive an LED (Light Emitting Diode) backlight.
2. Discussion of the Related Art
As information oriented society is developed, demands on image display devices increase in a variety of modes, and recently, many kinds of flat display devices, such as liquid crystal display devices, field emission display devices, plasma display panels, and light emitting display devices, are utilized.
Among the flat display devices, the liquid crystal display device displays a desired image as a liquid crystal panel having a matrix of pixel cells controls transmissivity of a light from the backlight unit.
Though fluorescent lamps are mostly used as a light source of the backlight unit in a related art, currently, an LED (Light Emitting Diode) is used as the light source of the backlight unit, which is favorable in view of power consumption, weight, brightness, and so on, instead of the fluorescent lamps according to a current trend of making the backlight unit smaller, thinner, and lighter than before.
The LED backlight unit has a combination of red, green, and blue or white LEDs, to emit the light by supplying a driving current to the LEDs. Accordingly, the backlight unit controls brightness of the backlight by controlling intensity of the driving current to the LEDs of the backlight.
However, since the LED backlight unit also becomes larger keeping pace with a trend in which the liquid crystal display device becomes larger, it is the present situation that reliability of the backlight unit enlarged thus becomes poor. In detail, the LED backlight unit controls the driving current to the LEDs with a plurality of LED driving ICs (Integrated Circuits). However, as the LED backlight unit becomes larger, a number of the LED driving ICs and a number of the LEDs matched to the LED driving ICs increase to cause variation of driving voltages (Currents) supplied to the LEDs greater.
Consequently, in the related art, each of the LED driving ICs is designed to have an internal storage device (EEPROM), a DAC Trimming circuit, and a plurality of fuses, for compensating an offset value (or a variation value) stored in advance according to an experimental value. However, since this design makes a driving method and an internal structure of each of the LED driving ICs complicate and a process for manufacturing the LED drive ICs complicate, this design has various problems such as increased cost and time for production of the LED drive ICs.
Moreover, mismatch in fabrication processes causes an offset between a receiver circuit and a comparator circuit which fall under chip interfaces of a semiconductor memory device. Consequently, a general semiconductor memory circuit has an offset adjusting circuit for adjustment of the offset.
A related art offset adjusting circuit will be described.
FIG. 1 illustrates a block diagram of a related art offset adjusting circuit.
Referring to FIG. 1, the related art offset adjusting circuit is provided with a sense amplifier 10, a correction voltage generating unit 20, and a control loading unit 30.
The sense amplifier 10 receives an input signal in and an offset voltage (off+, off−) for generating an output signal (out).
The correction voltage generating unit 20 receives the output signal (out) for generating a correction voltage (v+, v−) and a control signal (set). That is, the correction voltage (v+, v−) is varied until a voltage of the output signal (out) reaches to a target voltage level, and when the voltage of the output signal (out) reaches to the target voltage level, the correction voltage (v+, V−) being generated thus is maintained, and the control signal (set) is enabled.
The correction voltage generating unit 20 has a control unit 21 and a digital-to-analog converter (DAC) 22.
The control unit 21 receives the output signal (out) for generating a code signal and the control signal (set). That is, the control unit 21 makes up or down counting of the code signal until transition of a level of the output signal (out) occurs, and if the level of the output signal (out) transits, the control unit 21 makes up or down counting of the code signal no more, but makes the control signal (set) to enable.
The digital-to-analog converter 22 receives the code signal for generating the correction voltage (v+, v−). For an example, if the control unit 21 generates first to sixth code signals (code0˜code5), the digital-to-analog converter 22 generates six stages of positive correction voltages (v+) and negative correction voltages (v−) each having a fixed width of variation corresponding to the first to sixth codes (code0˜code5).
The control loading unit 30 receives the correction voltage (v+, v−) and the control signal (set) for generating the offset voltage (off+, off−). That is, if the control signal (set) is disabled, the control loading unit 30 provides the correction voltage (v+, v−) as the offset voltage (off+, off−), and, if the control signal (set) is enabled, the control loading unit 30 maintains the offset voltage (off+, off−) (See Korean Laid Open patent No. 10-2010-0041391).
However, the related art offset adjusting circuit has the following problems.
That is, since the related art offset adjusting circuit has a structure in which the offset of the reference voltage on one digital-to-analog converter is corrected, in order to apply the related art offset adjusting circuit to a system having a plurality of the digital-to-analog converters, it is required to add the related art offset adjusting circuits as many as a number of the digital-to-analog converters, causing a problem in that a plurality of the reference voltages corresponding to the number of digital-to-analog converters must be controlled.